The present invention relates to error correction, and more specifically, to correcting errors in register files in a processor.
In a processor, data may be stored in register files for processing instructions. Error detection and correction may be performed on the data. When an error is detected, an error correction process is initiated. Often, an error correction process requires a processing pipeline to be halted while the error is corrected. This results in lost processing time for the processor. In existing implementations, data operands stored in register files are read and checked for errors after instructions are issued by an issue queue. The issue queue tracks instructions with the use of instruction tags associated with each instruction. When an error is detected, processing is halted but the issue queue and processing logic must continue to track the status of instructions in progress. Unique data paths may also need to be implemented to transmit the data to an appropriate portion of the core for error correction processing. However, these operations are inefficient and complex.